In digital systems, digital data is typically handled with an associated clock signal. The clock signal is a square wave whose period is equal to the digital data bit period. The clock provides timing necessary to allow digital circuitry to operate on digital data. Basic clock functions include pacing and synchronizing the operations of a digital system, triggering registers and latches in digital circuits, and advancing counters.
When data are transmitted over a communications link, it is generally inefficient to also transmit the associated clock signal. This inefficiency has led to communications systems which transmit the data alone without the clock. Therefore, it is typical for fiber optic communication links to require that the clock signal at the receiving end of the link be extracted from the incoming data signal. To obtain the necessary clock at the receiving end, these systems employ clock recovery circuits. The clock recovery circuit derives the clock signal from the received digital data.
Conventional clock recovery circuits are often implemented using phase-locked loops. In phase-locked loops, a reference clock is generated at the frequency of the received data using a voltage controlled oscillator (VCO). A phase comparator compares the phase angle between the reference clock and a received data signal. The phase comparator outputs a control voltage which is a function of the phase angle between the generated clock and the received data signal. As the phase angle changes, the control voltage changes. The control voltage is fed back to the VCO to adjust the frequency of the reference clock. In this manner, the reference clock may be synchronized with the received data.
The phase-locked loop is often integrated onto a single chip along with other link adapter functions. These functions are described in a publication by J. F. Ewen et al. titled "Gb/s fiber Optic Link Adapter Chip Set," 1988 IEEE GaAs IC Symposium, pp. 11-14. This publication is hereby incorporated in its entirety into this disclosure.
In addition to clock recovery circuits, communications links often utilize demultiplexers at the receiving end. Demultiplexers segregate the serial data stream transmitted over the communications link into its component segments. These segments are typically defined by bytes or words that make up the serial stream. With a demultiplexer at the receiving end, multiple sets of data destined for different parallel processes, addresses, or components can be sent serially over a single communications link.
Conventional clock recovery circuits and demultiplexers operate at the full data rate of the signal transmitted over the communications link. Because the clock recovery and demultiplexing functions are fairly complex, they are difficult to perform at high data rates. As a result, for a given technology, the bandwidth of the communications link that they serve may be limited by the maximum data rate at which the clock recovery and demultiplexer circuits can operate.
This invention makes it possible to increase the maximum data rate of a communications link for a given technology. The present invention provides a combined clock recovery and front-end demultiplexer circuit that can be operated at half the received data rate or less. This allows the maximum data rate of the communications link of the present invention to be at least twice that of a conventional communications link for a given technology.